Silicon photonics startup Qiangyin Tech has recently secured tens of millions of RMB in an angel funding round led by Zhuhai Technology Industry Group, with participation from Zhuhai Zhengfang Group and Matrix Partners (Apex). The proceeds will be utilized for team expansion, chip tape-outs, and equipment acquisition. Founded in 2024, Qiangyin Tech focuses on Photonic Integrated Circuits (PIC), Optical IO (OIO), and Co-Packaged Optics (#CPO) solutions.
The founding team combines deep global and domestic chip design expertise. Founder Yi-Kei Li brings over 30 years of IC experience, formerly serving as Engineering VP at CUMEC and CTO of Cadence China. Co-founder and CTO Jingxiong Zhao previously served as Technical Director at CUMEC and technology lead at Intel and Cisco. Chief Scientist Craig Peterson was formerly the GM of Intel Microelectronics Center, with decades of experience designing processors and chipsets.
As generative AI and LLM training demand surges, computing clusters are scaling up with interconnect bandwidth transitioning rapidly to 1.6T and 3.2T. Traditional pluggable optical transceivers are hitting physical limits in power consumption and thermal dissipation. Deeply integrating optical engines with GPUs/CPUs via CPO and OIO has become the only viable path for ultra-high-speed data transmission. Qiangyin Tech targets this high-barrier sector starting with the key component: Micro-Ring Modulator (MRM).
Compared to traditional EML or MZM solutions, MRM features a micrometer-scale footprint and a drive voltage of less than 1V, making it ideal for high-density advanced packaging. Based on its self-developed single-channel 200G MRM, Qiangyin Tech has developed 1.6T silicon photonics chips and is designing Optical I/O Chiplets for chip-to-chip interconnects, bypassing high-power DSP chips to achieve extremely low system energy consumption.
To address the thermal sensitivity of MRM devices, Qiangyin has developed a proprietary real-time thermal control feedback and electrical equalization algorithm IP to ensure stability in harsh datacenter environments. Crucially, the company possesses proprietary silicon PDK (Process Design Kit) design capabilities and utilizes mature, domestic CMOS foundry lines, securing its supply chain. The firm has already entered the PoC stage with top domestic GPU vendors, co-developing TSV-based 3D stacking packaging solutions.
[AgentUpdate Depth Analysis] As AI Agent frameworks evolve from single, isolated instances to massive, real-time Multi-Agent Swarms, the communication overhead of collaborative reasoning places extreme demands on hardware. Traditional copper-based interconnects create severe latency and energy bottlenecks, capping the scalability of distributed Agent networks. By bringing optical signaling directly to the chip-to-chip level, Qiangyin's OIO and CPO solutions fundamentally tear down the "communication wall" between GPUs, enabling near-zero latency memory-pooling. This serves as a vital infrastructure catalyst, allowing tens of thousands of autonomous Agents to perform high-frequency state synchronization, cross-node coordination, and collective decision-making in real-time. Unlocking the physical limits of chip interconnects will be the pivotal prerequisite for the next generation of embodied and swarm-based AI Agent ecosystems.
